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3D Integration for VLSI SystemsFrom Pan Stanford
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Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV.
There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration. This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
- Sales Rank: #3479505 in Books
- Published on: 2011-09-26
- Original language: English
- Number of items: 1
- Dimensions: 9.50" h x 6.50" w x 1.00" l, 1.10 pounds
- Binding: Hardcover
- 350 pages
Review
"3D integration is expected to deliver performance improvement and functional enhancement in future integrated circuits and systems. This book covers a wide range of 3D integration topics authored by an impressive selection of experts. This is a great reference source for everyone following this promising technology."
―Prof. L. Rafael Reif - Provost and Maseeh Professor of Emerging Technology, MIT, USA
About the Author
Kuan-Neng Chen is an associate professor at the National Chiao Tung University in Taiwan. Steven Koester is a researcher at IBM. Chuan Seng Tan is an assistant professor at Nanyang Technological University in Singapore.
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